Global Placement Techniques for VLSI Physical Design Automation
نویسندگان
چکیده
VLSI physical design automation plays a vital role as we move to deep sub-micron designs below 0.18 microns. Power dissipation, performance and area are dominated by interconnections between elements in the circuit under consideration. Global Placement followed by iterative improvement placement (detailed placement) is the most robust, simple and successful approach in solving the placement problem. Initial solution produced by global placement will largely influence the convergence of the iterative improvement placement. In this paper, we compare the performance of several global placement algorithms for the VLSI standard cell circuit placement. The comparison is done at both flat level and hierarchical level using multilevel clustering technique.
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